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SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumfloat16x8_t[__arm_]vcreateq_f16(uint64_t a, uint64_t b)Vector manipulation / Create vector
Description
Creates a vector with a register representation the same as the concatenation of two 64-bit values.
Results
Qd result
This intrinsic compiles to the following instructions:

VMOV Qd[0], Rt0

VMOV Qd[1], Rt1

VMOV Qd[2], Rt2

VMOV Qd[3], Rt3

Argument Preparation
a register: [Rt0, Rt1]b register: [Rt2, Rt3]
Architectures
MVE